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1 ? fn9251.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006. all rights reserved. r 3 technology? is a trademark of intersil americas inc. all other trademarks mentioned are the property of their respective owners. ISL6261 single-phase core regulator for imvp-6 ? mobile cpus the ISL6261 is a single-phase buck regulator implementing lntel ? imvp-6 ? protocol, with embedded gate drivers. the heart of the ISL6261 is the patented r 3 technology?, intersil?s robust ripple regulator modulator. compared with the traditional multi-phase buck regulator, the r 3 technology? has faster transient response. this is due to the r 3 modulator commanding variable switching frequency during a load transient. lntel ? mobile voltage positioning (imvp) is a smart voltage regulation technology effectively reducing power dissipation in lntel ? pentium processors. to boost battery life, the ISL6261 supports dprslrvr (deeper sleep) function and maximizes the efficiency via automatically changing operation modes. at heavy load in the active mode, the regulator commands the continuous conduction mode (ccm) operation. when the cp u enters deeper sleep mode, the ISL6261 enables diode emulation to maximize the efficiency at light load. asserting the fde pin of the ISL6261 in deeper sleep mode will further decrease the switching frequency at light load and increase the regulator efficiency. a 7-bit digital-to-analog converter (dac) allows dynamic adjustment of the core output vo ltage from 0.300v to 1.500v. the ISL6261 has 0. 5% system volta ge accuracy over temperature. a unity-gain differential amplifier provides remote voltage sensing at the cpu die. this allows the voltage on the cpu die to be accurately measured and regulated per lntel ? imvp-6 specification. current sensing can be implemented through either lossless inductor dcr sensing or precise resistor sensing. if dcr sensing is used, an ntc thermistor network will thermally compensates the gain and the time constant variations caused by the inductor dcr change. features ? precision single-phase core voltage regulator - 0.5% system accuracy over temperature - enhanced load line accuracy ? internal gate driver with 2a driving capability ? microprocessor voltage identification input - 7-bit vid input - 0.300v to 1.500v in 12.5mv steps - support vid change on-the-fly ? multiple current sensing schemes supported - lossless inductor dcr current sensing - precision resistive current sensing ? thermal monitor ? user programmable switching frequency ? differential remote voltage sensing at cpu die ? overvoltage, undervoltage, and overcurrent protection ? pb-free plus anneal available (rohs compliant) ordering information part number (note) part marking temp range (c) package (pb-free) pkg. dwg. # ISL6261crz ISL6261crz -10 to +100 40 ld 6x6 qfn l40.6x6 ISL6261crz-t ISL6261crz -10 to +100 40 ld 6x6 qfn, t&r l40.6x6 ISL6261cr7z ISL6261cr7z -10 to +100 48 ld 7x7 qfn l48.7x7 ISL6261cr7z-t ISL6261cr7z -10 to +100 48 ld 7x7 qfn, t&r l48.7x7 ISL6261irz ISL6261irz -40 to +100 40 ld 6x6 qfn l40.6x6 ISL6261irz-t ISL6261irz -40 to +100 40 ld 6x6 qfn, t&r l40.6x6 ISL6261ir7z ISL6261ir7z -40 to +100 48 ld 7x7 qfn l48.7x7 ISL6261ir7z-t ISL6261ir7z -40 to +100 48 ld 7x7 qfn, t&r l48.7x7 note: intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet september 27, 2006
2 fn9251.1 september 27, 2006 pinouts ISL6261 (40 ld qfn) ISL6261 (48 ld qfn) 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 pgood 3v3 clk_en dprstp# dprslpvr vr_on vid6 vid5 vid4 vid3 vid2 vid1 vid0 vccp lgate vssp phase ugate boot nc fde pgd_in rbias vr_tt# ntc soft ocset vw comp fb vdiff vsen rtn droop dfb vo vsum vin vss vdd gnd pad (bottom) 3v3 clk_en# dprstp# dprslpvr 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 vr_on vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdiff vsen rtn droop dfb vo vsum vin vss vdd nc nc nc nc nc nc nc vccp lgate vssp phase ugate boot nc pgood fde pgd_in rbias vr_tt# ntc soft ocset vw comp fb nc gnd pad (bottom) ISL6261
3 fn9251.1 september 27, 2006 absolute maximum rati ngs thermal information supply voltage, vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7v battery voltage, vin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase). . . . . . . . . -0.3v to +7v(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to +9v(<10ns) phase voltage (phase) . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . . phase-0.3v (dc) to boot . . . . . . . . . . . . . .phase-5v (<20ns pulse width, 10j) to boot lgate voltage (lgate) . . . . . . . . . . . . . . -0.3v (dc) to vdd+0.3v . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd+0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd +0.3v) open drain outputs, pgood, vr_tt# . . . . . . . . . . . . -0.3 to +7v hbm esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kv thermal resistance (typical) ja (c/w) jc (c/w) 6x6 qfn package (notes 1, 2) . . . . . . 33 5.5 7x7 qfn package (notes 1, 2) . . . . . . 30 5.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300c recommended operating conditions supply voltage, vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 5% battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v to 21v ambient temperature . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c junction temperature . . . . . . . . . . . . . . . . . . . . . . .-10c to +125c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v dd = 5v, t a = -10c to +100c, unless otherwise specified. parameter symbol test conditions min typ max units input power supply +5v supply current i vdd vr_on = 3.3v - 3.1 3.6 ma vr_on = 0v - - 1 a +3.3v supply current i 3v3 no load on clk_en# pin - - 1 a battery supply current at vin pin i vin vr_on = 0, vin = 25v - - 1 a por (power-on reset) threshold por r v dd rising - 4.35 4.5 v por f v dd falling 3.85 4.1 - v system and references system accuracy %error (v cc_core ) no load, close loop, active mode, t a = 0 c to +100 c, vid = 0.75-1.5v -0.5 - 0.5 % vid = 0.5-0.7375v -8 - 8 mv vid = 0.3-0.4875v -15 - 15 mv rbias voltage r rbias r rbias = 147k 1.45 1.47 1.49 v boot voltage v boot 1.188 1.2 1.212 v maximum output voltage v cc_core (max) vid = [0000000] - 1.5 - v minimum output voltage v cc_core (min) vid = [1100000] - 0.3 - v vid off state vid = [1111111] - 0.0 - v channel frequency nominal channel frequency f sw r fset = 7k , v comp = 2v - 333 - khz adjustment range 200 - 500 khz amplifiers droop amplifier offset -0.3 0.3 mv error amp dc gain (note 3) a v0 -90 - db ISL6261
4 fn9251.1 september 27, 2006 error amp gain-bandwidth product (note 3) gbw c l = 20pf - 18 - mhz error amp slew rate (note 3) sr c l = 20pf - 5.0 - v/s fb input current i in(fb) - 10 150 na soft-start current soft-start current i ss -46 -41 -36 a soft geyserville current i gv |soft - ref|>100mv 175 200 225 a soft deeper sleep entry current i c4 dprslpvr = 3.3v -46 -41 -36 a soft deeper sleep exit current i c4ea dprslpvr = 3.3v 36 41 46 a soft deeper sleep exit current i c4eb dprslpvr = 0v 175 200 225 a gate driver driving capability (note 4) ugate source resistance r src(ugate) 500ma source current - 1 1.5 ugate source current i src(ugate) v ugate_phase = 2.5v - 2 - a ugate sink resistance r snk(ugate) 500ma sink current - 1 1.5 ugate sink current i snk(ugate) v ugate_phase = 2.5v - 2 - a lgate source resistance r src(lgate) 500ma source current - 1 1.5 lgate source current i src(lgate) v lgate = 2.5v - 2 - a lgate sink resistance r snk(lgate) 500ma sink current - 0.5 0.9 lgate sink current i snk(lgate) v lgate = 2.5v - 4 - a ugate to phase resistance r p(ugate) -1.1 - k gate driver switching timing (refer to timing diagram) ugate turn-on propagation delay t pdhu pv cc = 5v, output unloaded 20 30 44 ns lgate turn-on propagation delay t pdhl pv cc = 5v, output unloaded 7 15 30 ns bootstrap diode forward voltage v ddp = 5v, forward bias current = 2ma 0.43 0.58 0.67 v leakage v r = 16v - - 1 a power good and protection monitor pgood low voltage v ol i pgood = 4ma - 0.11 0.4 v pgood leakage current i oh p good = 3.3v -1 - 1 a pgood delay tpgd clk_en# low to pgood high 5.5 6.8 8.1 ms overvoltage threshold o vh v o rising above setpoint >1ms 160 200 240 mv severe overvoltage threshold o vhs v o rising above setpoint >0.5s 1.675 1.7 1.725 v ocset reference current i(rbias) = 10a 9.8 10 10.2 a oc threshold offset droop risi ng above ocset >120s -3.5 3.5 mv undervoltage threshold (vdiff-soft) uv f v o below set point for >1ms -360 -300 -240 mv logic thresholds vr_on, dprslpvr and pgd_in input low v il(3.3v) -- 1 v vr_on, dprslpvr and pgd_in input high v ih(3.3v) 2.3 - - v electrical specifications v dd = 5v, t a = -10c to +100c, unless otherwise specified. (continued) parameter symbol test conditions min typ max units ISL6261
5 fn9251.1 september 27, 2006 gate driver timing diagram leakage current on vr_on and pgd_in i il logic input is low -1 0 - a i ih logic input is high - 0 1 a leakage current on dprslpvr i il_dprslp dprslpvr logic input is low -1 0 - a i ih_dprslp dprslpvr logic input is high - 0.45 1 a dac(vid0-vid6), psi# and dprstp# input low v il(1.0v) --0.3 v dac(vid0-vid6), psi# and dprstp# input high v ih(1.0v) 0.7 - - v leakage current of dac(vid0- vid6) and dprstp# i il dprslpvr logic input is low -1 0 - a i ih dprslpvr logic input is high - 0.45 1 a thermal monitor ntc source current ntc = 1.3v 53 60 67 a over-temperature threshold v(ntc) falling 1.17 1.2 1.25 v vr_tt# low output resistance r tt i = 20ma - 5 9 clk_en# output levels clk_en# high output voltage v oh 3v3 = 3.3v, i = -4ma 2.9 3.1 - v clk_en# low output voltage v ol i clk_en# = 4ma - 0.18 0.4 v notes: 3. guaranteed by characterization. 4. guaranteed by design. electrical specifications v dd = 5v, t a = -10c to +100c, unless otherwise specified. (continued) parameter symbol test conditions min typ max units pwm ugate lgate 1v 1v t pdhl t rl t fu t ru t pdhu t fl ISL6261
6 fn9251.1 september 27, 2006 functional pin description fde forced diode emulation enable signal. logic high of fde with logic low of dprstp# forc es the ISL6261 to operate in diode emulation mode with an increased vw-comp voltage window. pgd_in digital input. suggest connec ting to mch_pwrgd, which indicates that vcc_mch voltage is within regulation. rbias a 147k resistor to vss sets internal current reference. vr_tt# thermal overload output indica tor with open-drain output. over-temperature pull-down resistance is 10. ntc thermistor input to vr_tt# circuit and a 60a current source is connected internally to this pin. soft a capacitor from this pin to gnd pin sets the maximum slew rate of the output voltage. th e soft pin is the non-inverting input of the error amplifier. ocset overcurrent set input. a resistor from this pin to vo sets droop voltage limit for oc trip. a 10a current source is connected internally to this pin. vw a resistor from this pin to comp programs the switching frequency (eg. 6.81k = 300khz). comp the output of the error amplifier. fb the inverting input of the error amplifier. vdiff the output of the differential amplifier. vsen remote core voltage sense input. rtn remote core voltage sense return. droop the output of the droop amplifie r. droop-vo voltage is the droop voltage. dfb the inverting input of the droop amplifier. vo an input to the ic that reports the local output voltage. 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 pgood 3v3 clk_en dprstp# dprslpvr vr_on vid6 vid5 vid4 vid3 vid2 vid1 vid0 vccp lgate vssp phase ugate boot nc fde pgd_in rbias vr_tt# ntc soft ocset vw comp fb vdiff vsen rtn droop dfb vo vsum vin vss vdd gnd pad (bottom) ISL6261
7 fn9251.1 september 27, 2006 vsum this pin is connected to one terminal of the capacitor in the current sensing r-c network. vin power stage input voltage. it is used for input voltage feed forward to improve the input line transient performance. vss signal ground. connect to controller local ground. vdd 5v control power supply. boot upper gate driver supply voltage. an internal bootstrap diode is connected to the vccp pin. ugate the upper-side mosfet gate signal. phase the phase node. this pin should connect to the source of upper mosfet. vssp the return path of the lower gate driver. lgate the lower-side mosfet gate signal. vccp 5v power supply for the gate driver. nc not connected. ground this pin in the practical layout. vid0, vid1, vid2, vi d3, vid4, vid5, vid6 vid input with vid0 as the le ast significant bit (lsb) and vid6 as the most significant bit (msb). vr_on vr enable pin. a logic high signal on this pin enables the regulator. dprslpvr deeper sleep enable signal. a logic high indicates that the microprocessor is in deeper sleep mode and also indicates a slow vo slew rate with 41 a discharging or charging the soft cap. dprstp# deeper sleep slow wake up signal. a logic low signal on this pin indicates that the microprocessor is in deeper sleep mode. clk_en# digital output for system pll clo ck. goes active 20s after pgd_in is active and vcore is within 10% of boot voltage. 3v3 3.3v supply voltage for clk_en#. pgood power good open-drain output. needs to be pulled up externally by a 680 resistor to vccp or 1.9k to 3.3v. ISL6261
8 fn9251.1 september 27, 2006 function block diagram figure 1. simplified functional block diagram of ISL6261 droop ocset vsum dfb droop 1 1 vo oc soft vo vsen vo rtn vdiff e/a soft fb 10ua vw comp modulator oc vin vsoft vw driver logic flt fault and pgood logic pgood monitor and logic mode control vr_on fde dprslpvr dprstp# vid0 vid1 vid2 vid3 vid4 vid5 vid6 dac pgd_in clk_en# pgood 3v3 rbias flt pgood gnd lgate vssp phase ugate boot vccp vccp vr_tt# ntc 1.22v 60ua vin vin vdd vccp vccp vss ISL6261
9 fn9251.1 september 27, 2006 simplified applicat ion circuit for dcr current sensing figure 2. ISL6261-based imvp-6? solution with inductor dcr current sensing vsum vo ocset dfb droop vssp lgate phase boot ugate vin vccp vdd 3v3 vw comp fb vdiff rbias ntc vr_tt# soft vids dprstp# dprslpvr fde pgd_in clk_en# vr_on pgood vr_tt# vid<0:6> dprstp# dprslpvr mch_pwrgd clk_enable# vr_on imvp6_pwrgd ISL6261 l o c o v o v in v +5 v +3.3 vss r 4 r 5 r 6 r 7 r 1 r 2 r 3 r 8 r 10 r 11 r 12 c 1 c 2 c 3 c 4 c 5 c 7 c 6 c 8 c 10 vsen vcc-sense rtn vss-sense c 9 r 9 ntc network ISL6261
10 fn9251.1 september 27, 2006 simplified applicati on circuit for resist ive current sensing figure 3. ISL6261-based imvp-6? solution with resistive current sensing vsum vo ocset dfb droop vssp lgate phase boot ugate vin vccp vdd 3v3 vw comp fb vdiff rbias ntc vr_tt# soft vids dprstp# dprslpvr fde pgd_in clk_en# vr_on pgood vr_tt# vid<0:6> dprstp# dprslpvr mch_pwrgd clk_enable# vr_on imvp6_pwrgd ISL6261 l o c o v o v in v +5 v +3.3 vss r 4 r 5 r 6 r 7 r 1 r 2 r 3 r 8 r 10 r 11 r 12 c 1 c 2 c 3 c 4 c 5 c 7 c 6 c 8 c 10 vsen vcc-sense rtn vss-sense r sen c 9 ISL6261
11 fn9251.1 september 27, 2006 theory of operation the ISL6261 is a single-phase regulator implementing intel ? imvp-6 ? protocol and includes an integrated gate driver for reduced system cost and boar d area. the ISL6261 imvp-6 ? solution provides optimum steady state and transient performance for microprocessor core voltage regulation applications up to 25a. implementation of diode emulation mode (dem) operation further enhances system efficiency. the heart of the ISL6261 is the patented r 3 technology?, intersil?s robust ripple regulator modulator. the r 3 ? modulator combines the best fe atures of fixed frequency and hysteretic pwm controllers whil e eliminating many of their shortcomings. the ISL6261 modulator internally synthesizes an analog of the inductor ripple current and uses hysteretic comparators on those signals to establish pwm pulses. operating on the large-amplitude and noise-free synthesized signals allows the ISL6261 to achieve lower output ripple and lower phase jitter than eith er conventional hysteretic or fixed frequency pwm controllers. unlike conventional hysteretic converters, the isl 6261 has an error amplifier that allows the controller to maintain 0.5% voltage regulation accuracy throughout the vid r ange from 0.75v to 1.5v. the hysteretic window voltage is with respect to the error amplifier output. ther efore the load current transient results in increased switching frequency, which gives the r 3 ? regulator a faster response than conventional fixed frequency pwm regulators. start-up timing with the controller?s vdd pin voltage above the por threshold, the start-up sequence begins when vr_on exceeds the 3.3v logic high threshold. in approximately 100 s, soft and vo start ramping to the boot voltage of 1.2v. at startup, the regulator always operates in continuous current mode (ccm), regardless of the control signals. during this interval, the soft cap is charged by a 41 a current source. if the soft capacitor is 20nf, the soft ramp will be 2mv/ s for a soft-start time of 600 s. once vo is within 10% of the boot voltage and pgd_in is high for six pwm cycles (20s for 300khz switching frequency), clk_en# is pulled low, and the soft cap is charged/discharged by approximate 200a and vo slews at 10mv/ s to the voltage set by the vid pins. in approximately 7ms, pgood is asserted h igh. figure 4 shows typical startup timing. pgd_in latch it should be noted that pgd_in going low will cause the converter to latch off. toggling pgd_in won?t clear the latch. toggling vr_on will clear it. this feature allows the converter to respond to ot her system voltage outages immediately. static operation after the startup sequence, the output voltage will be regulated to the value set by the vid inputs per table 1, which is presented in the lntel ? imvp-6 ? specification. the ISL6261 regulates the output voltage with 0.5% accuracy over the range of 0.7v to 1.5v. a true differential amplifier remotely senses the core voltage to precisely control the voltage at the microprocessor die. vsen and rtn pins are the inputs to the differential amplifier. as the load current increases from zero, the output voltage droops from the vid value pr oportionally to achieve the imvp-6 ? load line. the ISL6261 can sense the inductor current through the intrinsic series resistance of the inductors, as shown in figure 2, or through a precise resistor in series with the inductor, as shown in figure 3. the inductor current information is fed to the vsum pin, which is the non-inverting input to t he droop amplifier. the droop pin is the output of the dr oop amplifier, and droop-vo voltage is a high-bandwidth analog representation of the inductor current. this voltage is used as an input to a differential amplifier to achieve the imvp-6 ? load line, and also as the input to the ov ercurrent protection circuit. when using inductor dcr current sensing, an ntc thermistor is used to compensate the positive temperature coefficient of the copper winding resistance to maintain the load-line accuracy. the switching frequency of the ISL6261 controller is set by the resistor r fset between pins vw and comp, as shown in figures 2 and 3. vdd vr_on soft &vo pgd_in clk_en# imvp-vi pgood ~20us 100us vboot 2mv/us 10mv/us ~7ms figure 4. soft-start waveforms using a 20nf soft capacitor ISL6261
12 fn9251.1 september 27, 2006 table 1. vid table from intel imvp-6 specification vid6 vid5 vid4 vid3 vid2 vid1 vid0 vo (v) 00000001.5000 00000011.4875 00000101.4750 00000111.4625 00001001.4500 00001011.4375 00001101.4250 00001111.4125 00010001.4000 00010011.3875 00010101.3750 00010111.3625 00011001.3500 00011011.3375 00011101.3250 00011111.3125 00100001.3000 00100011.2875 00100101.2750 00100111.2625 00101001.2500 00101011.2375 00101101.2250 00101111.2125 00110001.2000 00110011.1875 00110101.1750 00110111.1625 00111001.1500 00111011.1375 00111101.1250 00111111.1125 01000001.1000 01000011.0875 01000101.0750 01000111.0625 01001001.0500 01001011.0375 01001101.0250 01001111.0125 01010001.0000 01010010.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.8500 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.6875 1 0 0 0 0 1 0 0.6750 1 0 0 0 0 1 1 0.6625 1 0 0 0 1 0 0 0.6500 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 table 1. vid table from intel imvp-6 specification (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 vo (v) ISL6261
13 fn9251.1 september 27, 2006 10101000.4500 10101010.4375 10101100.4250 10101110.4125 10110000.4000 10110010.3875 10110100.3750 10110110.3625 10111000.3500 10111010.3375 10111100.3250 10111110.3125 11000000.3000 11000010.2875 11000100.2750 11000110.2625 11001000.2500 11001010.2375 11001100.2250 11001110.2125 11010000.2000 11010010.1875 11010100.1750 table 1. vid table from intel imvp-6 specification (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 vo (v) 1 1 0 1 0 1 1 0.1625 1 1 0 1 1 0 0 0.1500 1 1 0 1 1 0 1 0.1375 1 1 0 1 1 1 0 0.1250 1 1 0 1 1 1 1 0.1125 1 1 1 0 0 0 0 0.1000 1 1 1 0 0 0 1 0.0875 1 1 1 0 0 1 0 0.0750 1 1 1 0 0 1 1 0.0625 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.0000 1 1 1 1 1 0 1 0.0000 1 1 1 1 1 1 0 0.0000 1 1 1 1 1 1 1 0.0000 table 1. vid table from intel imvp-6 specification (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 vo (v) table 2. control signal truth tables for operational modes of ISL6261 dprstp# fde dprslpvr operational mode vw-comp window voltage increase control signal logic 0 0 0 forced ccm 0% 0 0 1 diode emulation mode 0% 0 1 x enhanced diode emulation mode 33% 1 x x forced ccm 0% ISL6261
14 fn9251.1 september 27, 2006 high efficiency operation mode the operational modes of the ISL6261 depend on the control signal states of dprs tp#, fde, and dprslpvr, as shown in table 2. these control signals can be tied to lntel ? imvp-6 ? control signals to main tain the optimal system configuration for all imvp-6 ? conditions. dprstp# = 0, fde = 0 and dprslpvr = 1 enables the ISL6261 to operate in diode emulation mode (dem) by monitoring the low-side fet current. in diode emulation mode, when the low-side fet current flows from source to drain, it turns on as a synchronous fet to reduce the conduction loss. when the current reverses its direction trying to flow from drain to source, the ISL6261 turns off the low-side fet to prevent the output capacitor from discharging through the inductor, therefore eliminating the extra conduction loss. when dem is enabled, the regulator works in automatic discontinuous conduction mode (dcm), meaning that the regulator operates in ccm in heavy load, and operates in dcm in light load. dcm in light load decreases the switching frequency to increase efficiency. this mode can be used to support the deeper sleep mode of the microprocessor. dprstp# = 0 and fde = 1 enables the enhanced diode emulation mode (edem), which increases the vw-comp window voltage by 33%. this further decreases the switching frequency at light load to boost efficiency in the deeper sleep mode. for other combinations of dprstp#, fde, and dprslpvr, the ISL6261 operates in forced ccm. the ISL6261 operational modes can be set according to cpu mode signals to achieve the best performance. there are two options: (1) tie fde to dprslpvr, and tie dprstp# and dprslpvr to the corresponding cpu mode signals. this configuration enables edem in deeper sleep mode to increase efficiency. (2) tie fde to ?1? and dprstp# to ?0? permanently, and tie dprslpvr to the corresponding cpu mode signal. this configuration sets the regulator in edem all the time. the regulator will enter dcm based on load current. light-load efficiency is increased in both active mode and deeper sleep mode. cpu mode-transition sequences often occur in concert with vid changes. the ISL6261 employs carefully designed mode-transition timing to work in concert with the vid changes. the ISL6261 is equipped with in ternal counters to prevent control signal glitches fr om triggering unintended mode transitions. for example: cont rol signals lasting less than seven switching periods will not enable the diode emulation mode. dynamic operation the ISL6261 responds to vid changes by slewing to new voltages with a dv/dt set by the soft capacitor and the logic of dprslpvr. if c soft = 20nf and dprslpvr = 0, the output voltage will move at a maximum dv/dt of 10mv/ s for large changes. the maximum dv/dt can be used to achieve fast recovery from deeper sleep to active mode. if c soft = 20nf and dprslpvr = 1, the output voltage will move at a dv/dt of 2mv/ s for large changes. the slow dv/dt into and out of deeper sleep mode will minimize the audible noise. as the output voltage approaches the vid command value, the dv/dt moder ates to prevent overshoot. the ISL6261 is imvp-6 ? compliant for dprstp# and dprslpvr logic. intersil r 3 ? has an intrinsic voltage feed forward function. high-speed input voltage transients have little effect on the output voltage. intersil r 3 ? commands variable switching frequency during transients to achieve fast response. upon load application, the ISL6261 will transiently increase the switching frequency to deliver energy to the output more quickly. compared with steady state operation, the pwm pulses during load application are generated earlier , which effectively increases the duty cycle and the respon se speed of the regulator. upon load release, the ils6261 will transiently decrease the switching frequency to effectively reduce the duty cycle to achieve fast response. table 3. fault-protection summary of ISL6261 fault type fault duration prior to protection protecti on actions fault reset overcurrent fault 120 s pwm tri-state, pgood latched low vr_on toggle or vdd toggle way-overcurrent fault < 2 s pwm tri-state, pgood latched low vr_on toggle or vdd toggle overvoltage fault (1.7v) immediately low-si de fet on until vcore < 0.85v, then pwm tri- state, pgood latched low (ov-1.7v always) vdd toggle overvoltage fault (+200mv) 1ms pwm tri-state, pgood latched low vr_on toggle or vdd toggle undervoltage fault (-300mv) 1ms pwm tri-state, pgood latched low vr_on toggle or vdd toggle over-temperature fault (ntc<1.18) immediately vr_tt# goes high n/a ISL6261
15 fn9251.1 september 27, 2006 protection the ISL6261 provides overcurrent (oc), overvoltage (ov), undervoltage (uv) and over-temperature (ot) protections as shown in table 3. overcurrent is detected throu gh the droop voltage, which is designed as described in the ?component selection and application? section. the ocset resistor sets the overcurrent protection level. an overcurrent fault will be declared when the droop voltage exceeds the overcurrent set point for more than 120s. a way-overcurrent fault will be declared in less than 2s when the droop voltage exceeds twice the overcurrent set point. in both cases, the ugate and lgate outputs will be tri-stated and pgood will go low. the over-current condition is detected through the droop voltage. the droop voltage is equal to i core r droop , where r droop is the load line slope. a 10 a current source flows out of the ocset pin and creates a voltage drop across r ocset (shown as r 10 in figure 2). overcurrent is detected when the droop voltage exceeds the voltage across r ocset . equation 1 gives the selection of r ocset . for example: the desired over current trip level, i oc , is 30a, r droop is 2.1m , equation 1 gives r ocset =6.3k. undervoltage protection is independent of the overcurrent limit. a uv fault is declared when the output voltage is lower than (vid-300mv) for more than 1ms. the gate driver outputs will be tri-stated and pg ood will go low. note that a practical core regulator design usually trips oc before it trips uv. there are two levels of overvo ltage protection and response. an ov fault is declared when the output voltage exceeds the vid by +200mv for more than 1m s. the gate driver outputs will be tri-stated and pgood will go low. the inductor current will decay through the low-side fet body diode. toggling of vr_on or bringing vdd below 4v will reset the fault latch. a way-overvolt age (wov) fault is declared immediately when the output voltage exceeds 1.7v. the ISL6261 will latch pgood low and turn on the low-side fets. the low-side fets will remain on until the output voltage drops below approximately 0.85v, then all the fets are turned off. if the output voltage again rises above 1.7v, the protection process repeats. this mechanism provides maximum protection against a shorted high-side fet while preventing the output from ri nging below ground. toggling vr_on cannot reset the wov protection; recycling vdd will reset it. the wov detector is active all the time, even when other faults are declared, so the processor is still protected against the high-side fet leakage while the fets are commanded off. the ISL6261 has a thermal throttling feature. if the voltage on the ntc pin goes below t he 1.2v over-temperature threshold, the vr_tt# pin is pulled low indicating the need for thermal throttling to the syst em oversight processor. no other action is taken within the ISL6261. component selectio n and application soft-start and mode change slew rates the ISL6261 commands two different output voltage slew rates for various modes of operation. the slow slew rate reduces the inrush current during startup and the audible noise during the entry and the exit of deeper sleep mode. the fast slew rate enhances the system performance by achieving active mode regulation quickly during the exit of deeper sleep mode. the soft current is bidirectional ? charging the soft capacitor when the output voltage is commanded to rise, and discharging the soft capacitor when the output voltage is commanded to fall. figure 5 shows the circuitry on the soft pin. the soft pin, the non-inverting input of the e rror amplifier, is connected to ground through capacitor c soft . i ss is an internal current source connected to the soft pin to charge or discharge c soft . the ISL6261 controls the output voltage slew rate by connecting or disconnecting another internal current source i z to the soft pin, depending on the state of the system, i.e. startup or active mode, and the logic state on the dprslpvr pin. the soft-start current section of the electrical specification table shows the specs of these two current sources. i ss is 41 a typical and is used during startup and mode changes. when connected to the soft pin, i z adds to i ss to get a larger current, labelled i gv in the electrical specification table, on the soft pin. i gv is typically 200 a with a minimum of 175 a. the imvp-6 ? specification reveals the critical timing associated with regulating the output voltage. slewrate, a r i r droop oc ocset 10 = (eq. 1) c soft internal to ISL6261 error ampliflier v ref i ss i z figure 5. soft pin current sources for fast and slow slew rates ISL6261
16 fn9251.1 september 27, 2006 given in the imvp-6 ? specification, determines the choice of the soft capacitor, c soft , through the following equation: if slewrate is 10mv/ s, and i gv is typically 200 a, c soft is calculated as choosing 0.015 f will guarantee 10mv/ s slewrate at minimum i gv value. this choice of c soft controls the startup slew rate as well. one should expect the output voltage to slew to the boot value of 1.2v at a rate given by the following equation: selecting rbias to properly bias the ISL6261, a reference current needs to be derived by connecting a 147k, 1% tolerance resistor from the rbias pin to ground. this provides a very accurate 10 a current source from which ocset reference current is derived. caution should used in layout: this resistor should be placed in the close proximity of the rbias pin and be connected to good quality signal ground. do not connect any other components to this pin, as they will negatively impact the performance. capacitance on this pin may create instabilities and should be avoided. startup operation - clk_en# and pgood the ISL6261 provides a 3.3v logic output pin for clk_en#. the system 3.3v voltage source connects to the 3v3 pin, which powers internal circuitry that is solely devoted to the clk_en# function. the output is a cmos signal with 4ma sourcing and sinking capability. cmos logic eliminates the need for an external pull-up resistor on this pin, eliminating the loss on the pull-up resistor caused by clk_en# being low in normal operation. this prolongs battery run time. the 3.3v supply should be decoupled to digital ground, not to analog ground, for noise immunity. at startup, clk_en# remains high until 20 s after pgd_in going high, and vcc-core is re gulated at the boot voltage. the ISL6261 triggers an internal timer for the imvp6_pwrgd signal (pgood pin). this timer allows pgood to go high approximately 7ms after clk_en# goes low. static mode of operatio n - processor die sensing remote sensing enables the ISL6261 to regulate the core voltage at a remote sensing point, which compensates for various resistive voltage drops in the power delivery path. the vsen and rtn pins of the ISL6261 are connected to kelvin sense leads at the die of the processor through the processor socket. (the signal names are vcc_sense and vss_sense respectively). proc essor die sensing allows the voltage regulator to tightly control the processor voltage at the die, free of the inconsistencies and the voltage drops due slewrate i c gv soft = (eq. 2) () nf s mv a c soft 20 10 200 = = (eq. 3) s mv . f . a c i dt dv soft ss soft 8 2 015 0 41 = = = (eq. 4) figure 6. simplified voltage droop circuit with cpu-die voltage sensing and inductor dcr current sensing dcr droop dfb vsum c o v o l esr droop vo ocset 10ua i phase r ocset r s 1 oc r ntc r series r drp1 r drp2 c n r par vsen rtn 1 0~10 r opn1 r opn2 vcc-sense vss-sense 1000pf 1000pf 330pf to processor socket kelvin conections vdiff internal to ISL6261 ISL6261
17 fn9251.1 september 27, 2006 to layouts. the kelvin sense technique provides for extremely tight load line regulation at the processor die side. these traces should be laid out as noise sensitive traces. for optimum load line regulation performance, the traces connecting these two pins to the kelvin sense leads of the processor should be laid out away from rapidly rising voltage nodes (switching nodes) and other noisy traces. common mode and differential mode filters are recommended as shown in figure 6. the recommended filter resistance range is 0~10 so it does not interact with the 50k input resistance of the differential amplifier. th e filter resistor may be inserted between vcc-sense and the vsen pin. another option is to place one between vcc- sense and the vsen pin and another between vss-sense and the rtn pin. the need of these filters also depends on the actual board layout and the noise environment. since the voltage feedback is se nsed at the processor die, if the cpu is not installed, the regulator will dr ive the output voltage all the way up to damage the output capacitors due to lack of output voltage feedback. ropn1 and ropn2 are recommended, as shown in figure 6, to prevent this potential issue. ropn1 and ropn2, typically ranging 20~100 , provide voltage feedback fr om the regulator local output in the absence of the cpu. setting the switching frequency - fset the r 3 modulator scheme is not a fixed frequency pwm architecture. the switching frequency increases during the application of a load to improve transient performance. it also varies slightly depending on the input and output voltages and output current, but this variation is normally less than 10% in continuous conduction mode. resistor r fset (r 7 in figure 2), connected between the vw and comp pins of the ISL6261, sets the synthetic ripple window voltage, and therefore sets the switching frequency. this relationship between the resistance and the switching frequency in ccm is approximately given by the following equation. in diode emulation mode, the ISL6261 stretches the switching period. the switchin g frequency decreases as the load becomes lighter. diode emulation mode reduces the switching loss at light load, which is important in conserving battery power. voltage regulator thermal throttling lntel ? imvp-6 ? technology supports thermal throttling of the processor to prevent catastrophic thermal damage to the voltage regulator. the ISL6261a features a thermal monitor sensing the voltage across an externally placed negative temperature coefficient (ntc) thermistor. proper selection and placement of the ntc thermi stor allows for detection of a designated temperature rise by the system. figure 7 shows the circuitry associated with the thermal throttling feature of the ISL6261. at low temperature, sw1 is on and sw2 connects to the 1.20v side. the total current going into the ntc pin is 60a. the voltage on the ntc pin is higher than 1.20v threshol d voltage and the comparator output is low. vr_tt# is pulled up high by an external resistor. temperature increase will decrease the ntc thermistor resistance. this decreases the ntc pin voltage. when the ntc pin voltage drops below 1.2v, the comparator output goes high to pull vr_tt# low, signalling a thermal throttle. in addition, sw1 turns off and sw2 connects to 1.23v, which decreases the ntc pin current by 6a and increases the threshold voltage by 30mv. the vr_tt# signal can be used by th e system to change the cpu operation and decrease the power consumption. as the temperature drops, the ntc pin voltage goes up. if the ntc pin voltage exceeds 1.23v, vr_tt# will be pulled high. figure 8 illustrates the temper ature hysteresis feature of vr_tt#. t 1 and t 2 (t 1 >t 2 ) are two threshold temperatures. vr_tt# goes low when the temperature is higher than t 1 and goes high when the temperature is lower than t 2 . ()( ) 33 2 29 0 ) ( . . s period k ? r fset ? = (eq. 5) figure 7. circuitry associated with the thermal throttling feature internal to ISL6261 v ntc 54ua 6ua sw2 r ntc r s vr_tt# 1.23v 1.20v sw1 ntc t ( o c) t 1 t 2 logic_0 logic_1 vr_tt# t ( o c) t 1 t 2 logic_0 logic_1 vr_tt# figure 8. vr_tt# temperature hysterisis ISL6261
18 fn9251.1 september 27, 2006 the ntc thermistor?s resistance is approximately given by the following formula: t is the temperature of the ntc thermistor and b is a constant determined by the thermistor material. t o is the reference temperature at which the approximation is derived. the most commonly used t o is 25 c. for most commercial ntc thermistors, there is b = 2750k, 2600k, 4500k or 4250k. from the operation principle of vr_tt#, the ntc resistor satisfies the following equation group: from equation 7 and equation 8, the following can be derived: substitution of equation 6 into equation 9 yields the required nominal ntc resistor value: in some cases, the constant b is not accurate enough to approximate the resistor value; manufacturers provide the resistor ratio information at different temperatures. the nominal ntc resistor value may be expressed in another way as follows: where is the normalized ntc resistance to its nominal value. the normalized resistor value on most ntc thermistor datasheets is based on the value at 25 c. once the ntc thermistor resistor is determined, the series resistor can be derived by: once r ntcto and r s is designed, the actual ntc resistance at t 2 and the actual t 2 temperature can be found in: one example of using equations 10, 11 and 12 to design a thermal throttling circuit wit h the temperatur e hysteresis 100 c to 105 c is illustrated as follows. since t 1 = 105 c and t 2 =100 c, if we use a panasonic ntc with b = 4700, equation 9 gives the required ntc nominal resistance as the ntc thermistor datasheet gives the resistance ratio as 0.03956 at 100 c and 0.03322 at 105 c. the b value of 4700k in panasonic datasheet only covers up to 85 c; therefore, using equation 11 is more accurate for 100 c design and the required ntc nominal resistance at 25 c is 438k . the closest ntc resistor value from manufacturers is 470k . so equation 12 gives the series resistance as follows: the closest standard value is 4.42k . furthermore, equation 13 gives the ntc resistance at t 2 : the ntc branch is designed to have a 470k ntc and a 4.42k resistor in series. the part number of the ntc thermistor is ertj0ev474j. it is a 0402 package. the ntc thermistor should be placed in the spot that gives the best indication of the temperature of the voltage regulator. the actual temperature hysteretic window is approximately 105 c to 100 c. ) 273 1 273 1 ( ) ( + ? + ? ? = to t b e ntcto r t ntc r (eq. 6) k ? a v . r ) (t r s ntc 20 60 20 1 1 = = + (eq. 7) k ? . a v . r ) (t r s ntc 78 22 54 23 1 2 = = + (eq. 8) k ? . ) (t r ) (t r ntc ntc 78 2 1 2 = ? (eq. 9) ) t ( b ) t ( b ) t ( b ntcto e e e k ? . r o 273 1 273 1 273 1 1 2 78 2 + ? + ? + ? ? ? = (eq. 10) ) (t r ) (t r k ? . r ntc ntc ntcto 1 2 78 2 ? = (eq. 11) ) t ( r ntc 1 20 60 20 1 1 ntc_t ntc s r k ? ) (t r a v . r ? = ? = (eq. 12) 1 _ 2 _ 78 . 2 t ntc t ntc r k r + = (eq. 13) 273 ) 273 ( 1 ) ln( 1 1 2 _ _ 2 ? + + = o ntcto t ntc actual t r r b t (eq. 14) k ? r ntc_to 431 = = ? = ? = k k k r k r c ntc s 39 . 4 61 . 15 20 20 105 _ = + = k r k r t ntc t ntc 39 . 18 78 . 2 1 _ 2 _ ISL6261
19 fn9251.1 september 27, 2006 static mode of operation - static droop using dcr sensing the ISL6261 has an internal differential amplifier to accurately regulate the voltage at the processor die. for dcr sensing, the process to compensate the dcr resistance variation takes several iterative steps. figure 2 shows the dcr sensing method. figure 9 shows the simplified model of the droop circuitry. the inductor dc current generates a dc voltage drop on the inductor dcr. equation 15 gives this relationship. an r-c network senses the voltage across the inductor to get the inductor current information. r n represents the ntc network consisting of r ntc , r series and r par . the choice of r s will be discussed in the next section. the first step in droop load line compensation is to choose r n and r s such that the correct droop voltage appears even at light loads between the vsum and vo nodes. as a rule of thumb, the voltage drop across the r n network, v n , is set to be 0.5-0.8 times v dcr . this gain, defined as g1, provides a fairly reasonable amount of light load signal from which to derive the droop voltage. the ntc network resistor value is dependent on the temperature and is given by: g1, the gain of v n to v dcr , is also dependent on the temperature of the ntc thermistor: the inductor dcr is a function of the temperature and is approximately given by in which 0.00393 is the temperat ure coefficient of the copper. the droop amplifier output voltage divided by the total load current is given by: r droop is the actual load line slope. to make r droop independent of the inductor tem perature, it is desired to have: where g 1target is the desired ratio of v n /v dcr . therefore, the temperature characteristics g 1 is described by: for different g1 and ntc the rmistor preference, intersil provides a design spreadsheet to generate the proper value of r ntc , r series , r par . figure 9. equivalent model fo r droop circuit using dcr sensing droop dfb vsum droop vo ocset 10ua r s 1 oc r drp1 r drp2 c n internal to ISL6261 dcr i o v dcr r ocset vo r ntc r series r n (r ntc +r series ) r+r series ntc +r par r par r par dcr i v o dcr = (eq. 15) par ntc series par ntc series n r r r r r r t r + + ? + = ) ( ) ( (eq. 16) (eq. 17) s n n r t r t r t g + = ) ( ) ( ) ( 1 )) 25 ( * 00393 . 0 1 ( ) ( 25 ? + ? = t dcr t dcr c (eq. 18) (eq. 19) droopamp droop k t dcr (t) g r ? ? = ) ( 1 et t g t t g arg 1 1 )) 25 ( * 00393 . 0 1 ( ) ( ? ? + ? (eq. 20) ) 25 t ( * 00393 . 0 1 ( g ) t ( g et arg t 1 1 ? + = (eq. 21) ISL6261
20 fn9251.1 september 27, 2006 r drp1 (r 11 in figure 2) and r drp2 (r 12 in figure 2) sets the droop amplifier gain, according to equation 22: after determining r s and r n networks, use equation 23 to calculate the droop resistances r drp1 and r drp2 . r droop is 2.1mv/a per lntel ? imvp-6 ? specification. the effectiveness of the r n network is sensitive to the coupling coefficient between the ntc thermistor and the inductor. the ntc thermistor should be placed in close proximity of the inductor. to verify whether the ntc netw ork successfully compensates the dcr change over temperatur e, one can apply full load current, and wait for the thermal steady state, and see how much the output voltage deviates from the initial voltage reading. good thermal compensatio n can limit the drift to less than 2mv. if the output voltage decreases when the temperature increases, that ra tio between the ntc thermistor value and the rest of the resistor divider network has to be increased. following the evaluati on board value and layout of ntc placement will minimize the engineering time. the current sensing traces should be routed directly to the inductor pads for accurate dcr voltage drop measurement. however, due to layout imperfection, the calculated r drp2 may still need slight adjustment to achieve optimum load line slope. it is recommended to adjust r drp2 after the system has achieved thermal equilibrium at full load. for example, if the max current is 20a, one should apply 20a load current and look for 42mv output voltage droop. if the voltage droop is 40mv, the new value of r dpr2 is calculated by: for the best accuracy, the effective resistance on the dfb and vsum pins should be identical so that the bias current of the droop amplifier does not cause an offset voltage. the effective resistance on the vsum pin is the parallel of r s and r n , and the effective resistance on the dfb pin is the parallel of r drp1 and r drp2 . dynamic mode of operation ? droop capacitor design in dcr sensing figure 10 shows the desired waveforms during load transient response. v core needs to be as square as possible at i core change. the v core response is determined by several factors, namely the choice of output inductor and output capacitor, the compensator design, and the droop capacitor design. the droop capacitor refers to c n in figure 9. if c n is designed correctly, its voltage will be a high-bandwidth analog voltage of the inductor current. if c n is not designed correctly, its voltage will be distorted from the actual waveform of the inductor current and worsen the transient response. figure 11 shows the transient response when c n is too small. v core may sag excessively upon load application to create a system failure. figure 12 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there will be excessive overshoot if a load occurs during this time, which may potentially hurt the cpu reliability. the current sensing network consists of r n , r s and c n . the effective resistance is the parallel of r n and r s . the rc time constant of the current sensi ng network needs to match the l/dcr time constant of the inductor to get correct representation of the inductor current waveform. equation 25 shows this equation: 1 2 1 drp drp droopamp r r k + = (eq. 22) 1 2 ) 1 ) 25 ( 1 ( drp o droop drp r c g dcr r r ? ? ? = (eq. 23) 1 2 1 _ 2 ) ( 40 42 drp drp drp new drp r r r mv mv r ? + = (eq. 24) i core v core i core v core v core v core = i core r droop figure 10. desired load transient response waveforms i core v core v core figure 11. load transient response when c n is too small i core v core v core figure 12. load transient response when c n is too large n s n s n c r r r r dcr l ? ? ? ? ? ? ? ? + = (eq. 25) ISL6261
21 fn9251.1 september 27, 2006 solving for cn yields for example: l = 0.45 h, dcr = 1.1m , r s =7.68k , and r n =3.4k since the inductance and the dcr typically have 20% and 7% tolerance respectively, the l/dcr time constant of each individual inductor may not perfectly match the rc time constant of the current sensing network. in mass production, this effect will make the transient response vary a little bit from board to board. compar ed with potential long-term damage on cpu reliability, an immediate system failure is worse. so it is desirable to avoid the waveforms shown in figure 11. it is recommended to choose the minimum c n value based on the maximum inductance so only the scenarios of figures 10 and 12 may happen. it should be noted that, after calculation, fine-tuning of c n value may still be needed to account for board parasitics. c n also needs to be a high-grade cap like x7r with low tolerance. another good option is the npo/cog (cla ss-i) capacitor, featuring only 5% tolerance and very good thermal characteristics. but the npo/cog caps are only available in small capacitance values. in order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier need to be scaled up 10x to reduce the capacitance by 10x. attention needs to be paid in balancing the impedance of droop amplifier. dynamic mode of operation - compensation parameters the voltage regulator is equivalent to a voltage source equal to vid in series with the output impedance. the output impedance needs to be 2.1m in order to achieve the 2.1mv/a load line. it is highly recommended to design the compensation such that the regulator output impedance is 2.1m . a type-iii compensator is recommended to achieve the best performance. intersil provides a spreadsheet to design the compensator parameters. figure 13 shows an example of the spreadsheet. after the user inputs the parameters in the blue font, the spreadsheet will calculate the recommended compensator parameters (in the pink font), and show the loop gain curv es and the regulator output impedance curve. the loop gain curves need to be stable for regulator stability, and the impedance curve needs to be equal to or smaller than 2.1m in the entire frequency range to achieve good transient response. the user can choose the actual resistor and capacitor values based on the recommendation and input them in the spreadsheet, then see the actual loop gain curves and the regulator output impedance curve. caution needs to be used in choosing the input resistor to the fb pin. excessively high resistance will cause an error to the output voltage regulation due to the bias current flowing in the fb pin. it is recommended to keep this resistor below 3k. droop using discrete resistor sensing - static/dynamic mode of operation figure 3 shows a detailed schematic using discrete resistor sensing of the inductor current. figure 14 shows the equivalent circuit. since the cu rrent sensing resistor voltage represents the actual inductor current information, r s and c n simply provide noise filtering. the most significant noise comes from the esl of the current sensing resistor. a low low esl sensing resistor is strongly recommended. the recommended r s is 100 and the recommended c n is 220pf. since the current sensing resistance does not appreciably change with temperature, the ntc network is not needed for thermal compensation. droop is designed the same way as the dcr sensing approach. the voltage on the current sensing resistor is given by the following equation: equation 21shows the droop ampl ifier gain. so the actual droop is given by solving for r drp2 yields: for example: r droop =2.1m . if r sen = 1m and r drp1 = 1k, easy calculation gives that r drp2 is 1.1k. the current sensing traces shou ld be routed directly to the current sensing resistor pads for accurate measurement. however, due to layout imperfections, the calculated r drp2 may still need slight adjustment to achieve optimum load line slope. it is recommended to adjust r drp2 after the system has achieved thermal equilibrium at full load. s n s n n r r r r dcr l c + = (eq. 26) nf k k parallel h c n 174 ) 4 . 3 , 68 . 7 ( 0011 . 0 45 . 0 = = (eq. 27) o sen rsen i r v ? = (eq. 28) ? ? ? ? ? ? ? ? + ? = 1 2 1 drp drp sen droop r r r r (eq. 29) ? ? ? ? ? ? ? ? ? ? = 1 1 2 sen droop drp drp r r r r (eq. 30) ISL6261
22 fn9251.1 september 27, 2006 figure 13. an example of ISL6261 compensation spreadsheet vss ISL6261
23 fn9251.1 september 27, 2006 droop dfb vsum droop vo ocset 10ua r s 1 oc r drp1 r drp2 c n internal to ISL6261 r i o v rsen sen r ocset vo figure 14. equivalent model for droop ci rcuit using discrete resistor sensing typical performance (data taken on ISL6261 eval1 rev. c evaluation board) figure 15. ccm efficiency, vid = 1.1v, v in1 =8v, v in2 = 12.6v and v in3 =19v figure 16. ccm load line and the spec, vid = 1.1v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 17. dem efficiency, vid = 0.7625v, v in1 =8v, v in2 = 12.6v and v in3 =19v figure 18. dem load line and the spec, vid = 0.7625v, v in1 =8v, v in2 = 12.6v and v in3 = 19v ISL6261
24 fn9251.1 september 27, 2006 figure 19. enhanced dem efficiency, vid = 0.7625v, v in1 =8v, v in2 = 12.6v and v in3 =19v figure 20. enhanced dem load line, vid = 0.7625v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 21. enhanced dem efficiency, vid = 1.1v, v in1 = 8v, v in2 = 12.6v and v in3 = 19v figure 22. enhanced dem load line, vid = 1.1v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 23. soft-start, v in = 19v, io = 0a, vid = 1.5v, ch1: vr_on, ch2: vo, ch4: phase figure 24. soft-start, v in = 19v, io = 0a, vid = 1.1v, ch1: vr_on, ch2: vo, ch4: phase typical performance (data taken on ISL6261 eval1 rev. c evaluation board) (continued) 5v/div 0.5v/div 10v/div ISL6261
25 fn9251.1 september 27, 2006 figure 25. v boot to vid, v in = 19v, io = 2a, vid = 1.5v, ch1: pgd_in, ch2: vo, ch3: clk_en#, ch4: phase figure 26. v boot to vid, v in = 19v, io = 2a, vid = 0.7625v, ch1: pgd_in, ch2: vo, ch3: pgood, ch4: clk_en figure 27. clk_en and pgood assertion delay, v in =19v, io=2a, vid=1.1v, ch1: clk_en#, ch2: vo, ch3: pgood, ch4: phase figure 28. shut down, v in = 19v, io = 0.5a, vid = 1.5v, ch1: vr_on, ch2: vo, ch3: pgood, ch4: phase figure 29. soft start inrush current, v in =19v, io = 0.5a, vid = 1.1v, ch1: droop-vo (2.1mv = 1a), ch2: vo, ch3: vcomp, ch4: phase figure 30. v in transient test, v in =8 ? 19v, io = 2a, vid = 1.1v, ch1: vo, ch3: v in , ch4: phase typical performance (data taken on ISL6261 eval1 rev. c evaluation board) (continued) 5v/div 0.2v/div 10v/div 5v/div 5v/div 0.2v/div 5v/div 5v/div 5v/div 0.5v/div 10v/div 5v/div 7.5ms ISL6261
26 fn9251.1 september 27, 2006 figure 31. c4 entry/exit, v in = 12.6v, io = 0.7a, hfm vid = 1.1v, lfm vid = 0.9v, c4 vid = 0.7625v, fde = dprslpvr, ch1: dprstp#, ch2: vo, ch3: dprslpvr/fde, ch4: phase figure 32. vid toggling, v in = 12.6v, io= 0.7a, hfm vid = 1.1v, lfm vid = 0.9v, ch1: soft, ch2: vo, ch3: vcomp, ch4: phase figure 33. load step up response in ccm, v in = 8v, io = 2a ? 20a at 100a/us, vid = 1.1v, ch1: io, ch2: vo, ch3: vcomp, ch4: phase figure 34. load step down response in ccm v in = 8v, io = 20a ? 2a at 100a/us, vid = 1.1v, ch1: io, ch2: vo, ch3: vcomp, ch4: phase figure 35. load transient response in ccm v in = 8v, io = 2a ?? 20a, vid = 1.1v, ch1: io, ch2: vo, ch3: vcomp, ch4: phase figure 36. load transi ent response in enhanced dem, v in = 8v, io = 2a ?? 20a, vid = 1.1v, ch1: io, ch2: vo, ch3: vcomp, ch4: phase typical performance (data taken on ISL6261 eval1 rev. c evaluation board) (continued) 100a/us 50a/us 100a/us 50a/us 100a/us 50a/us ISL6261
27 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9251.1 september 27, 2006 figure 37. load transient response in enhanced dem, v in = 8v, io = 2a ?? 20a, vid = 1.1v, ch1: io, ch2: vo, ch3: vcomp, ch4: phase figure 38. load transient response in enhanced dem, v in =8v, io=2a ?? 20a, vid = 1.1v, ch1: io, ch2: vo, ch3: vcomp, ch4: phase figure 39. overcurrent protection, v in = 12.6v, io = 0a ? 28a, vid = 1.1v, ch1: droop-vo (2.1mv = 1a), ch2: vo, ch3: pgood, ch4: phase figure 40. overvoltage (>1.7v) protection, v in = 12.6v, io = 2a, vid = 1.1v, ch2: vo, ch3: pgood, ch4: phase typical performance (data taken on ISL6261 eval1 rev. c evaluation board) (continued) 100a/us 50a/us 120us ISL6261
28 fn9251.1 september 27, 2006 ISL6261 eval1 rev. c eval uation board schematic run lgate1 trace parallel to trace connecting note: pgnd1 and source of q3 and q4. off on 1 5 ? pgood 47pf 1000pf ssl_lxa3025igc p7 38 39 3 dnp rbias dnp 10 p6 c17 c20 c9 390pf 150pf r23 r19 5.49k 464k 4 3 dnp p8 p4 p5 vcc_prm r4 ocset vw r103 fde dprstp# sd05h0sk 10k r10 pgd_in 2n7002 2 510 vsssense 0 r6 0 r5 10k s1 c6 r15 c15 r17 dnp r31 dnp vr_tt pgd_in 7 5 p13 j15 2 lgate gnd_power c29 0.01uf ugate dfb dnp 0 r12 c11 p12 vdiff1 p15 r28 10k ntc +3.3v p2 1uf r24 2.21k vcc_prm droop 10uf 2 q5 +3.3v r39 +5v c30 10uf 22 pgood +3.3v 4 dprslpvr r21 psi# 10k r14 10k r3 dprstp# p19 mst7_spst 3v3 u6 j10 psi# 0.015uf c10 r25 1 3 2 s4 r45 3 2 1 j19 3 2 1 1 j8 r46 c18 c16 8 17 25 19 12 4 16 18 34 32 31 30 29 28 20 27 23 6 13 24 2 7 5 21 26 1 10 41 14 15 9 c28 p32 9 8 7 6 5 3 2 1 p29 2 1 j9 p26 c23 c14 c19 r47 1 p23 p24 p25 p27 p28 p31 p33 2 1 j17 c24 r33 r34 2 1 j16 c27 c26 r35 p3 p9 c2 r11 p10 1 p1 p14 1 p16 p18 p20 c31 j3 j4 j2 j1 c3 r20 c8 r16 r22 r30 c7 c21 r8 r7 c12 r13 r9 r1 1 r44 2 3 1 d3 r38 r37 r36 r41 r42 r32 r40 9 8 6 4 3 2 14 13 12 11 10 1 u1 clk_en# dprslpvr +3.3v 147k dnp 5v 10 3.3v +3.3v 10uf vid4 comp ISL6261 eval1 controller jia wei mar-14-05 vcore vccsense gnd_power 510 dnp 330pf vsum 1k 0.1uf 0 1000pf dnp soft 0 fb 0 0 0 1uf 0 boot phase 499 0 1uf dprslpvr vr_on vid0 vid5 vid3 vid2 vid1 vid6 10k 10k vin +5v +3.3v vr_on1 10k 10k vr_on 10 10k 10k 10k 10k 10k +3.3v 100 1000pf 0.22uf r2 6.34k 6.81k 5.23k 0.12uf 0.068uf r43 10k fde 33 35 36 37 40 10k r18 p34 ISL6261cr c13 p17 r29 c25 p22 10k 11 p21 rtn vsen dnp p11 330pf p30 3.57k 4.53k r27 8200pf 1x3 1 2 3 fde ntc vr_tt rbias soft vr_on dprstp vid5 vid1 vid0 vdiff fb ep vid2 vid3 vid4 vid6 clk_en pgood 3v3 vsen ocset vw dfb vo rtn droop vsum vin vss vdd dprslpvr pgd_in comp vccp nc boot ugate phase vssp lgate title: engineer: drawn by: sheet: date: rev: of a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 5 on on on on on 1 3 2 4 out out in in in in in in in in out in out out in in in out in out in in in in in in 1 2 1 2 3 4 5 6 7 13 12 11 10 9 8 14 1x3 1 2 3 1 2 1 2 red grn 1 2 1 2 ISL6261
29 fn9251.1 september 27, 2006 ISL6261 eval1 rev. c eval uation board schematic (continued) c90 c44 c43 330uf 330uf 330uf c41 330uf c89 c40 330uf 330uf c36 22uf 22uf 22uf c52 22uf c37 r54 r53 0.45uh 2 bus wire 1 dnp dnp r60 c33 dnp p38 j6 p41 lgate phase ugate 0 r48 p40 vsssense 2 j22 0 c4 vin irf7821 q4 2 5 ISL6261 eval1 power stage jia wei mar-14-05 0.1uf 0.1uf c1 2 p37 q2 j20 3 4 2 3 4 1 j21 3 4 1 p35 p36 c35 1 1 c91 q3 irf7821 irf7832 d2 q1 1 10uf 1uf c32 dnp r49 l1 dnp r52 vsum 7.68k r51 p39 0 r50 j5 10uf vcc_prm vccsense 0.1uf c34 1 j14 c64 22uf c58 22uf c65 22uf c59 22uf c70 22uf c66 c60 22uf c46 22uf c53 22uf c47 22uf c54 22uf c48 22uf 22uf c38 22uf c67 22uf c61 22uf c68 22uf c62 22uf c71 22uf c69 22uf c63 22uf c55 22uf c49 22uf c56 22uf c50 22uf c39 22uf c42 22uf c57 22uf c51 22uf c45 vcore gnd_power j13 1 0.22uf boot c5b 10uf c5 irf7832 56uf r82 56uf r83 out in out in out out in in in out in title: engineer: drawn by: sheet: date: rev: of a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 ISL6261
30 fn9251.1 september 27, 2006 ISL6261 eval1 rev. c eval uation board schematic (continued) af7 w21 v6 v21 t6 t21 r6 r21 n6 n21 m6 m21 k6 k21 j6 j21 g21 b26 f9 f7 f20 f18 f17 f15 f14 f12 f10 e9 e7 e20 e18 e17 e15 e13 e12 e10 d9 d18 d17 d15 d14 d12 d10 c9 c18 c17 c15 c13 c12 c10 b9 b7 b20 b18 b17 b15 b14 b12 b10 af9 af20 af18 af17 af15 af14 af12 af10 ae9 ae20 ae18 ae17 ae15 ae13 ae12 ae10 ad9 ad7 ad18 ad17 ad15 ad14 ad12 ad10 ac9 ac7 ac18 ac17 ac15 ac13 ac12 ac10 ab9 ab7 ab20 ab18 ab17 ab15 ab14 ab12 ab10 aa9 aa7 aa20 aa18 aa17 aa15 aa13 aa12 aa10 a9 a7 a20 a18 a17 a15 a13 a12 a10 socket1 ae7 y6 y3 y24 y21 w4 w26 w23 w1 v5 v25 v22 v2 u6 u3 u24 u21 t4 t26 t23 t1 r5 r25 r22 r2 p6 p3 p24 p21 n4 n26 n23 n1 m5 m25 m22 m2 l6 l3 l24 l21 k4 k26 k23 k1 j5 j25 j22 j2 h6 h3 h24 h21 g4 g26 g23 g1 f8 f5 f25 f22 f2 f19 f16 f13 f11 e8 e6 e3 e24 e21 e19 e16 e14 e11 d8 d4 d26 d23 d19 d16 d13 d11 d1 c8 c5 c25 c22 c2 c19 c16 c14 c11 b8 b6 b24 b21 b19 b16 b13 b11 af8 af6 af3 af24 af21 af19 af16 af13 af11 ae8 ae4 ae26 ae23 ae19 ae16 ae14 ae11 ae1 ad8 ad5 ad25 ad22 ad2 ad19 ad16 ad13 ad11 ac8 ac6 ac3 ac24 ac21 ac19 ac16 ac14 ac11 ab8 ab4 ab26 ab23 ab19 ab16 ab13 ab11 ab1 aa8 aa5 aa25 aa22 aa2 aa19 aa16 aa14 aa11 a8 a4 a26 a23 a19 a16 a14 a11 socket1 ae2 af2 ae3 af4 ae5 af5 ad6 y5 y4 y26 y25 y23 y22 y2 y1 w6 w5 w3 w25 w24 w22 w2 v4 v3 v26 v24 v23 u5 u4 u25 u23 u22 u2 t5 t3 t25 t24 t22 t2 r4 r3 r24 r23 r1 p5 p4 p26 p25 p23 p22 p2 p1 n5 n3 n25 n24 n22 n2 m4 m3 m26 m24 m23 m1 l5 l4 l26 l25 l23 l22 l2 l1 k5 k3 k25 k24 k22 k2 j4 j3 j26 j24 j23 j1 h5 h4 h26 h25 h23 h22 h2 h1 g6 g5 g3 g25 g24 g22 g2 f6 f4 f3 f26 f24 f23 f21 f1 e5 e4 e26 e25 e23 e22 e2 e1 d7 d6 d5 d3 d25 d24 d22 d21 d20 d2 c7 c6 c4 c3 c26 c24 c23 c21 c20 c1 b5 b4 b3 b25 b23 b22 b2 b1 af26 af25 af23 af22 af1 ae25 ae24 ae22 ae21 ad4 ad3 ad24 ad23 ad21 ad20 ad1 ac5 ac4 ac26 ac25 ac23 ac22 ac20 ac2 ac1 ab6 ab5 ab3 ab25 ab24 ab22 ab21 ab2 aa6 aa4 aa3 aa26 aa24 aa23 aa21 aa1 a6 a5 a3 a25 a24 a22 a21 ae6 ad26 v1 u1 u26 r26 socket1 5 3 intel_impv6 vccsense vcore vsssense vid5 vid1 vid4 psi# vid6 vid3 vid0 vid2 intel_impv6 intel_impv6 gnd_power socket ISL6261 eval1 mar-14-05 jia wei in out out out out out out title: engineer: drawn by: sheet: date: rev: of a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 out in out out out vccp vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vccp vccp vccp vccp vccp vccp vccp vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vccp vccp vcc vcc vcc vcc vcc vccp vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vccp vccp vcc vcc vcc vcc vcc vccp vccp vccp vcca vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vccsense vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vsssense vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss s vid5 s s s s s s s s s comp3 s s comp1 s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s comp0 comp2 s s s s s s s s s s s s s s s s s s s s s s gtlref psi vid6 vid3 vid4 vid2 vid0 vid1 s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s ISL6261
31 fn9251.1 september 27, 2006 ISL6261 eval1 rev. c eval uation board schematic (continued) on off 0.12 0.1 d1 3 1 4 3 2 j23 1 2 s5 r76 r75 3 1 2 q15 j12 c81 r72 r73 r74 2 3 1 r71 j11 c80 2 1 3 q14 7 1 8 6 4 3 5 2 u5 gnd_power 2n7002 499 49.9k +12v hip2100 10uf 249 249 bav99 huf76129d3s gnd_power 1uf +12v vcore in +12v hi lo hs ho li vss vdd hb ISL6261
32 fn9251.1 september 27, 2006 ISL6261 eval1 rev. c eval uation board schematic (continued) reset psi# psi# dprslp loop direct delay mode trans r106 pgd_in dnp dnp r68 13 0 r67 r104 29 6 clk_en# pic16f874 18 c78 1uf +3.3v_gey dnp +3.3v_gey r63 +3.3v_gey j25 dnp 3 27 1 bav99 p45 p43 0.01uf c79 10k 12 7 c85 26 14 0.1uf r65 +3.3v_gey c74 20 hc540 0.1uf c75 evqpa s6 1 2 3 4 j29 1 2 10k 10k r64 4 r69 5 jia wei mar-14-05 ISL6261 eval1 geyserville transition gen. 5 5 mst7_spst mst7_spst mst7_spst +3.3v +3.3v_gey hc540 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 0.1uf 10k 10k 10k 10k 10k 10k 0 10k 15pf hcm49 ac04 dnp 0 0 1uf bav99 15pf psi# vid0 vid1 vid2 vid3 vid4 vid5 vid6 dprstp# dprslpvr 0 +3.3v_gey evqpa 10k evqpa 0.1uf 10k +3.3v_gey 0.1uf +3.3v_gey evqpa +3.3v vr_on1 u8 1 10 11 12 13 14 2 3 4 5 6 7 8 9 u9 1 10 11 12 13 14 2 3 4 5 6 7 8 9 u7 1 10 11 12 13 14 2 3 4 5 6 7 8 9 r55 j24 1 2 u2 2 3 4 5 6 9 1 19 10 20 18 17 16 11 u3 2 3 4 5 6 7 8 1 19 10 20 18 17 16 15 14 12 11 u4 2 3 4 5 6 7 8 9 1 19 10 18 17 16 15 14 13 12 11 r56 r57 r58 r59 r61 r62 c87 u11 1 2 s2 s7 1 2 3 4 c76 1 2 c73 c72 u10 12 13 33 34 30 31 19 24 8 9 10 11 14 15 16 17 32 35 37 42 43 1 38 39 40 41 2 3 4 25 7 28 r80 c88 r79 u12 1 3 5 9 11 13 7 14 2 4 6 8 10 12 p44 c86 s9 1 3 2 j7 1 2 3 r77 s3 1 3 2 r70 r78 c84 s8 1 2 3 4 j28 1 2 r81 r87 r90 r93 r96 r99 r82 r85 r88 r94 r97 r100 r83 r86 r89 r92 r95 r98 r101 r102 hc540 15 r105 p42 23 22 21 20 36 44 13 9 r91 r84 10k 8 0.1uf 2 c77 r66 10k +3.3v_gey +3.3v_gey 0 out in out out out out out out out out out out out title: engineer: drawn by: sheet: date: rev: of a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1x3 1 2 3 vcc 6y 6a 5y 5a 4a 4y 1a 1y 2a 2y 3a 3y gnd 1 2 3 4 5 6 7 13 12 11 10 9 8 14 osc2 mclr rb0 rb1 rb2 rb4 rb3 rb5 rb6 rb7 nc nc ra0 ra4 ra3 ra2 ra1 ra5 osc1 vdd vdd rc1 rc0 rc2 rc7 rc6 rc5 rc4 rc3 nc nc rd0 re0 rd7 rd6 rd4 rd5 rd3 rd2 rd1 re1 re2 vss vss 1 2 1 2 3 4 5 6 7 13 12 11 10 9 8 14 1 2 3 4 5 6 7 13 12 11 10 9 8 14 y4 a5 g1 a1 a3 a4 a6 a7 a8 y8 y7 y6 y5 y3 y2 y1 g2 gnd vcc a2 y4 a5 g1 a1 a3 a4 a6 a7 a8 y8 y7 y6 y5 y3 y2 y1 g2 gnd vcc a2 1 2 y4 a5 g1 a1 a3 a4 a6 a7 a8 y8 y7 y6 y5 y3 y2 y1 g2 gnd vcc a2 1 2 1 2 ISL6261
33 fn9251.1 september 27, 2006 ISL6261 package outline drawing l40.6x6 40 lead quad flat no-lead plastic package rev 2, 9/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between .015mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (4x) 0.15 index area pin 1 a 6.00 b 6.00 31 36x 0.50 4.5 4x 40 pin #1 index area bottom view 40x 0 . 4 0 . 1 20 b 0.10 11 ma c 4 21 4 . 10 0 . 15 0 . 90 0 . 1 c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. detail "x" 0 . 05 max. 0 . 2 ref c 5 side view 1 10 30 typical recommended land pattern ( 5 . 8 typ ) ( 4 . 10 ) ( 36x 0 . 5 ) ( 40x 0 . 23 ) ( 40x 0 . 6 ) 6 6 top view 0 . 23 +0 . 07 / -0 . 05
34 fn9251.1 september 27, 2006 ISL6261 package outline drawing l48.7x7 48 lead quad flat no-lead plastic package rev 3, 9/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between .015mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 7.00 b a 7.00 (4x) 0.15 index area pin 1 top view pin #1 index area 44x 0.50 4x 5.5 48 37 4. 30 0 . 15 1 36 25 48x 0 . 40 0 . 1 4 m 0.10 c ab 13 24 bottom view 12 5 0 . 2 ref 0 . 00 min. 0 . 05 max. detail "x" c 0 . 90 0 . 1 base plane see detail "x" c c 0.08 seating plane c 0.10 side view typical recommended land pattern 6 6 ( 6 . 80 typ ) ( 4 . 30 ) ( 48x 0 . 60 ) ( 44x 0 . 5 ) ( 48x 0 . 23 ) 0.23 +0.07 / -0.05

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